VLSI Design of On-Line Add/Multiply Algorithms

IINTRODUCTION On-line arithmetic principles were introduced by Ercegovac and Trivedi in 1977 [1][2]. In this arithmetic, operands are represented in a redundant number system such as Avizienis' signed digit systems [3]. They are serially introduced starting from the most significant digit (MSD). Consequently, the result MSDs are first obtained, and can thus be exploited while computation is still in progress. This allows dynamically pushing the computation precision to any extent [4][5][6]. To obtain the first digit of the output of an operator, a small number, called the operator on-line delay, of digits of the input operands are needed. From then on, a new result digit is generated for each new operand digit. Another important feature of on-line architectures is the operator latency which expresses the transition time between the operator inputs and outputs. The question is to know what compromise to make between these two features. In fact, one can optimise one of them at the expense of the other. Designers have to choose which feature should be preferred according to the operator utilisation. In the following, we assume that the numbers are represented in a radix-two signed-digit number system, with digits -1, 0 and 1. Each Signed Binary Digit (SBD) c is represented by two bits c+ and csuch that c = c+ c. This encoding, called borrow-save, is quite convenient for operator design. We first expose the basic VLSI tools used to implement on-line arithmetic algorithms. Then we give some examples of synthesis concerning on-line addition and multiplication. As a straightforward application we will discuss, in section IV, the realisation of a VLSI circuit for on-line polynomial computing. IIVLSI TOOLS II-1 The PPM cell Given three inputs a, b and c, the PPM cell (for Plus Plus Minus) generates two outputs e and f such that 2e f = a + b c. Fig. 1 represents the PPM symbol, logic equations and schematic. e = Maj (a, b, c) f = a ⊕ b ⊕ c a b c e f + + +